Overview

The FLORA floorplanner

FLORA is a floorplanner that optimizes the allocation of hardware accelerators on the FPGA fabric.

The problem of floorplanning for dynamic partial reconfiguration consists in geometrically placing reconfigurable regions (RRs) within the available area of the FPGA. Producing a feasible floorplan means satisfying the resource requirements of the RRs while respecting the specific vendor-related technological constraints. In addition to feasibility, an optimal floorplan minimizes some performance metrics such as FPGA resource consumption or the maximum wire-length between RRs.

The resource requirement of RRs consists in ensuring that each RR must contain at least the maximum amount of resources required by all the reconfigurable modules that it hosts. Some of the vendor-related constraints on the Xilinx FPGAs include

  • RRs must be rectangular;
  • Vertical boundaries of RRs must not split back-to-back interconnect tiles;
  • Horizontal boundaries of RRs must be aligned with clock regions if the reconfigurable module is to be reset after reconfiguration;
  • RRs must not include some components of the FPGA (for 7 series devices this includes clock modifying logic, I/O related components, ICAP, XADC, etc…).

One of the major challenges in floorplanning automation is to adequately model the non-uniform distribution of heterogeneous resources on the fabric, since the model is tightly coupled with the definition of the aforementioned constraints.

FLORA solves the floorplanning automation problem and produces optimal floorplans for RRs by leveraging Mixed-Integer Linear Programming (MILP) optimization based on a fine-grained layout model of the computing resources (i.e., CLBs, BRAMs and DSPs) and system resources (i.e., interconnects, different functional blocks etc…) on the FPGA.

The key to the fine-grained resource layout model in FLORA is the resource distribution fingerprint. The resource fingerprint is generated by overlaying a 2D discrete Cartesian coordinate system on the FPGA fabric whose origin is the at the bottom-left corner. Each unit on the x-axis denotes a column of resources (CLB, BRAM, DSP, interconnects, central clock column) while each unit on the y-axis represents a single clock region that is fused with the horizontally adjacent clock regions. The resource finger-print in FLORA is the representation of the resources in the first clock region with a piece-wise constant function. It also contains the locations of all the forbidden components on the fabric.

The inputs to FLORA are the FPGA resource fingerprint, the resource requirements of the RRs, and the parameters the designer wants to optimize. Inside FLORA, the resource fingerprint and the resource requirements are translated into a set of MILP constraints and solved using a solver.

The output of FLORA is a constraint file (e.g., an .xdc file for Xilinx’s Vivado) that describes the layout of each RR according to the syntax specified by the design tool provided by the vendor. Before the generation of the final constraint file, FLORA provides an additional visualization tool that allows the designer to inspect the generated floorplan.